SHIEH Jia-Lin | Department of Electrical Engineering, National Central University
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概要
Department of Electrical Engineering, National Central University | 論文
- Platform-Based Design for the Low Complexity and High Performance De-Interlacing System
- Platform-Based Design for the Low Complexity and High Performance De-Interlacing System
- A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder(Digital Signal Processing)
- VLSI Design for Embedded Digital Watermarking JPEG Encoder Based on Digital Camera System(VLSI Design Technology and CAD)
- Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits