Nakamura Kunio | Semiconductor Leading Edge Technologies, Inc. (Selete), Tsukuba, Ibaraki 305-8569, Japan

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Semiconductor Leading Edge Technologies, Inc. (Selete), Tsukuba, Ibaraki 305-8569, Japan | 論文

• Trench Sidewall Elimination Effect on Line-to-Line Leakage Current in Scalable Porous Silica ($k= 2.1$)/Cu Interconnect Structure
• High-Etching-Selectivity Barrier SiC ($k
• Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
• Analysis of Dose-Pitch Matrices of Line Width and Edge Roughness of Chemically Amplified Fullerene Resist

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