Nara Yasuo | Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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- Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japanの論文著者
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan | 論文
- Interfacial Reaction of TiN/HfSiON Gate Stack in High-Temperature Annealing for Gate-First Metal–Oxide–Semiconductor Field-Effect Transistors
- Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-$k$ Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain