CHUANG Chi-Nan | the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National

スポンサーリンク

概要

関連著者

Liu Shen-iuan
The Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National
CHUANG Chi-Nan
the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National
Chuang Chi-nan
The Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National

著作論文

A 1 V Phase Locked Loop with Leakage Compensation in 0.13μm CMOS Technology (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)

スポンサーリンク