A 1 V Phase Locked Loop with Leakage Compensation in 0.13μm CMOS Technology (Low Power Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)

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概要

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• In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phaselocked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-μm CMOS process. The power consumption is 3 mW and the die area is 0.27×0.3mm^2.

• 社団法人電子情報通信学会の論文

著者

• Liu Shen-iuan

  The Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National

• CHUANG Chi-Nan

  the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National

• Chuang Chi-nan

  The Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National

関連論文

• A 1 V Phase Locked Loop with Leakage Compensation in 0.13μm CMOS Technology (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)

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