Kobayashi Hiromi | The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku | 論文
- Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic(Novel Device Architectures and System Integration Technologies)
- A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(New System Paradigms for Integrated Electronics)
- A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
- Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms
- A Robust 3D Face Recognition Algorithm Using Passive Stereo Vision