CHENG Kuo-Hsing | Dept. EE, National Central University
スポンサーリンク
概要
関連著者
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CHENG Kuo-Hsing
Dept. EE, National Central University
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Cheng Kuo‐hsing
National Central Univ. Jungli Twn
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Liao Huan-sen
Dept. Of Electrical Engineering Tamkang University
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CHENG Shun-Wen
VLSI Lab., Dept. EE, Tamkang University
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Cheng Kuo-hsing
Dept. Of Electrical Engineering Tamkang University
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Cheng Shun-wen
Vlsi Lab. Dept. Ee Tamkang University
著作論文
- A Programmable Delay Element for Low-Power PLL Applications
- 64-Bit High-Performance Power-Aware Conditional Carry Adder Design(Integrated Electronics)