Kawamura Hidenori | Graduate School of Information Science and Technology, Hokkaido University

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Graduate School of Information Science and Technology, Hokkaido University | 論文

• A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(New System Paradigms for Integrated Electronics)
• A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
• Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
• Fabrication of double-dot single-electron transistor in silicon nanowire
• Novel-Functional Single-Electron Devices Using Silicon Nanodot Array

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