CHEN Chen | National Laboratory for Parallel and Distributed Processing, National University of Defense Technology

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• 同名の論文著者
• National Laboratory for Parallel and Distributed Processing, National University of Defense Technologyの論文著者

National Laboratory for Parallel and Distributed Processing, National University of Defense Technology | 論文

• High performance sparse matrix-vector multiplication on FPGA
• Parallel Sparse Cholesky Factorization on a Heterogeneous Platform
• FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic
• Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
• Transpose-free Variable-Size FFT Accelerator Based On-chip SRAM

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