High performance sparse matrix-vector multiplication on FPGA
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概要
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This paper presents the design and implementation of a high performance sparse matrix-vector multiplication (SpMV) on field-programmable gate array (FPGA). By proposing a new storage format to compress the indexes of non-zero elements by exploiting the substructure of the sparse matrix, our SpMV implementation on a reconfigurable computing platform with a multi-channel memory subsystem is capable of obtaining similar performance by using a single FPGA to that of a highly optimized BFS implementation on a commercial heterogeneous system containing four FPGAs.
著者
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Dou Yong
National Laboratory For Parallel And Distribution Processing National University Of Defense Technology
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Zou Dan
National Laboratory for Parallel and Distributed Processing, National University of Defense Technology
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Ni Shice
National Laboratory for Parallel and Distributed Processing, National University of Defense Technology
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Guo Song
National Laboratory for Parallel and Distributed Processing, National University of Defense Technology
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Dou Yong
National Laboratory for Parallel and Distributed Processing, National University of Defense Technology
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