SHIOTA Sayaka | Faculty of System Design, Tokyo Metropolitan University

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Faculty of System Design, Tokyo Metropolitan University | 論文

• Note on programmable on-product clock generation (OPCG) circuitry for low power aware delay test (ディペンダブルコンピューティング)
• Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
• A parameter memorization-free lossless data hiding method with flexible payload size
• Encryption of Composite Multimedia Contents for Access Control(Image,Multimedia and Mobile Signal Processing)
• An Efficient Reversible Image Authentication Method

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