Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

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概要

• 論文の詳細を見る
• Institute of Physicsの論文
• 2014-03-24

著者

• Koike Hiroki

  Center For Microelectronic Systems Kyushu Institute Of Technology

• Koike Hiroki

  Center for Spintronics Integrated Systems, Tohoku University, Sendai 980-8577, Japan.

関連論文

• An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O
• Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

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