Fabrication and Demonstration of 3-nm-Channel-Length Junctionless Field-Effect Transistors on Silicon-on-Insulator Substrates Using Anisotropic Wet Etching and Lateral Diffusion of Dopants

概要

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Junctionless field-effect transistors (JL-FETs) with a 3 nm channel length are fabricated on silicon-on-insulator (SOI) substrates using simple process techniques. The anisotropic etching of Si crystals by alkaline solution is utilized to form V-grooves and to define nanometer-scale channel structures. Ultrathin channels created on the SOI have a 3 nm channel length that is determined by the edge of V-grooves. Dopants are introduced by ion implantation at the source and drain regions and diffused into the channel region at a high temperature and by long-period annealing. V-groove JL-FETs thus fabricated show superior performances by scaling the thickness of the SOI channel toward 1 nm and less. Through the measurement of many V-groove JL-FETs and a simulation study, it is clarified that the management of channel thickness with atomic-scale precision is indispensable for sub-10 nm FETs.
2013-04-25