Fabrication of Parylene-Based High-Aspect-Ratio Suspended Structure Using a Silicon-on-Insulator Wafer

スポンサーリンク

概要

• 論文の詳細を見る

• In this study, we fabricated a parylene-based high-aspect-ratio suspended structure using a definition silicon-on-insulator (SOI) wafer. In this process a silicon micro trench is used as a mold, in which parylene beams are fabricated through the deposition and removal of parylene in multiple stages, after which the structure is released in a hydrofluoric acid solution to remove the buried oxide layer in the SOI wafer, followed by supercritical drying for preventing stiction. Compared with conventional processes, our process exploits the advantages of the SOI wafer to eliminate the extra oxide mask or the support wafer for structure release, thereby reducing process complexity and cost. The reactive-ion etching (RIE) lag effect and notch effect are also considered in this paper. In this study, we fabricated the test devices of the parylene beams without voids inside, which were integrated with a thermal actuator and a comb-drive actuator. Compared with silicon suspended beams, the flexibility of the parylene beams and the uniformity of device thickness are suitable for actuators with large in-plane displacements and low driving forces, and also for sensors with high sensitivity.

• 2013-03-25

著者

• Kuo Wen-Cheng

  Department of Mechanical and Automation Engineering, National Kaohsiung First University of Science and Technology, Nanzih, Kaohsiung 811, Taiwan

• Chen Chen-Wei

  Department of Mechanical and Automation Engineering, National Kaohsiung First University of Science and Technology, Nanzih, Kaohsiung 811, Taiwan

関連論文

• Single-Run Single-Mask Inductively-Coupled-Plasma Reactive-Ion-Etching Process for Fabricating Suspended High-Aspect-Ratio Microstructures
• Fabrication of Parylene-Based High-Aspect-Ratio Suspended Structure Using a Silicon-on-Insulator Wafer

スポンサーリンク