Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

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概要

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• A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density ($D_{\text{it}}$). It is worthwhile to note that the $D_{\text{it}}$ as well as the GIDL current is a still meaning parameter to analyze the data retention time.

• 2011-04-25

著者

• Ryu Seong-Wan

  Semiconductor R&D Division, Hynix Semiconductor Inc., Icheon, Gyeonggi-do 467-701, Korea

• Jeong Jae-Goan

  Semiconductor R&D Division, Hynix Semiconductor Inc., Icheon, Gyeonggi-do 467-701, Korea

• Cha Seonyong

  Semiconductor R&D Division, Hynix Semiconductor Inc., Icheon, Gyeonggi-do 467-701, Korea

• Yoo Minsoo

  Semiconductor R&D Division, Hynix Semiconductor Inc., Icheon, Gyeonggi-do 467-701, Korea

• Choi Deuksung

  Division of Electronics and Information Engineering, Yeungnam College of Science and Technology, Daegu 705-703, Korea

関連論文

• Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

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