A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

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概要

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• This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal–oxide–semiconductor (CMOS) node and beyond.

• 2010-04-25

著者

• Chrong Jung

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Tsai Yi-Hung

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Yang Hsiao-Lan

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Lin Wun-Jie

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Ya-Chin King

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Yi-Hung Tsai

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Wun-Jie Lin

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

• Hsiao-Lan Yang

  Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan

関連論文

• A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

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