A Highly Scalable Capacitor-Less Cell Having a Doubly Gated Vertical Channel

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概要

• 論文の詳細を見る

• A double-gate transistor structure with a vertical channel is proposed and demonstrated via three-dimensional device simulations to be well suited for dynamic random access memory (DRAM) application. The double-gate transistor structure with a vertical channel (DGVC) cell occupies 4F2 area, provides for good retention characteristics (with immunity to disturbances), and is compatible with conventional memory process flows for stand-alone DRAM memories. In comparison with previous cell designs, the DGVC cell is more scalable, so that it is an excellent candidate for the continued scaling of DRAM technology to the 22-nm node and beyond.

• 2010-04-25

著者

• Wookhyun Kwon

  EECS Department, University of California, Berkeley, CA 94720-1770, U.S.A.

• Tsu-Jae King

  EECS Department, University of California, Berkeley, CA 94720-1770, U.S.A.

• Kwon Wookhyun

  EECS Department, University of California, Berkeley, CA 94720-1770, U.S.A.

• Liu Tsu-Jae

  EECS Department, University of California, Berkeley, CA 94720-1770, U.S.A.

関連論文

• A Highly Scalable Capacitor-Less Cell Having a Doubly Gated Vertical Channel

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