Experiments and Simulation of Stress Induced Voiding Dependence on Upper Metal Cap Layer in Cu/Low-$k$ Interconnects

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概要

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• We conducted stress-induced voiding (SIV) experiments on Cu/low-$k$ interconnect with different upper metal cap layers to evaluate their reliability impact. We showed the cap layer of upper metal had strong effect on the SIV performance. A finite element analysis is applied to simulate the stress fields inside these via test structures. We explained the different SIV performance of these via schemes with the stress results.

• 2009-04-25

著者

• Liang James

  United Microelectronics Corp., No. 3, Li-Hsin Rd. II, Science-Based Industrial Park, Hsinchu 30077, Taiwan

• Su Kuan

  United Microelectronics Corp., No. 3, Li-Hsin Rd. II, Science-Based Industrial Park, Hsinchu 30077, Taiwan

• Lin Mingte

  United Microelectronics Corp., No. 3, Li-Hsin Rd. II, Science-Based Industrial Park, Hsinchu 30077, Taiwan

関連論文

• Experiments and Simulation of Stress Induced Voiding Dependence on Upper Metal Cap Layer in Cu/Low-$k$ Interconnects

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