Raised Source/Drain on Different Integration Schemes for Sub-Micro CMOS

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概要

• 論文の詳細を見る

• The performance of raised source/drain by selective epitaxial growth (SEG) using two different integration sequences were compared in this article. It was observed that inserting SEG layer after source/drain annealing provided more benefits on reduction of junction leakage and parasitic resistance and 12% $I_{\text{on}}$ improvement at $I_{\text{off}}=10$ nA on PMOS.

• 2005-04-15

著者

• Chiang Yi-ying

  United Microelectronics Corporation (umc) Central R&d Division

• Lee Yi-chia

  United Microelectronics Corporation (umc) Central R&d Division

• Cheng Ellen

  United Microelectronics Corporation (umc) Central R&d Division

• Lee Yi-Chia

  United Microelectronics Corporation (UMC), Central R&D Division, No. 18, Nanke 2nd Rd., Tainan Science Park, Sinshih Township, Tainan County 741, Taiwan, ROC.

• Chiang Yi-Ying

  United Microelectronics Corporation (UMC), Central R&D Division, No. 18, Nanke 2nd Rd., Tainan Science Park, Sinshih Township, Tainan County 741, Taiwan, ROC.

関連論文

• Raised Source/Drain on Different Integration Schemes for Sub-micro CMOS
• Raised Source/Drain on Different Integration Schemes for Sub-Micro CMOS

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