Design of Switching-Mode CMOS Frequency Multipliers in Sub-Terahertz Regime

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概要

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• Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195GHz tripler having a hair-pin filter is designed to maximize 3rd harmonics with -14.8dB of conversion gain (CG) from Pin=+13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG=-16dB from two +13dBm of the balanced I/Q driving signals in a 65nm digital CMOS process.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Park Jung-Dong

  Graduate of School of Engineering, University of California

関連論文

• Design of Switching-Mode CMOS Frequency Multipliers in Sub-Terahertz Regime

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