Si nanowire MOSFETs Techniques for High Performance and Low Power LSIs
スポンサーリンク
概要
- 論文の詳細を見る
In this work, we demonstrate high-performance silicon tri-gate nanowire transistor (NW Tr.) with NW width less than 15 nm. We successfully reduced the parasitic resistance of NW Tr. by raised source/drain extensions with thin spacers with < 10 nm. Furthermore, we introduced stress memorization technique (SMT) to NW Tr. And much larger mobility increase is obtained in NW Tr. than in planar Tr. The threshold voltage variability of NW Tr. is studied and the threshold voltage variability in NW Tr. is reduced compared to planar SOI Tr. due to gate grain alignment. The performance of NW Tr. CMOS circuits under the low voltage operation is investigated by using the Spice model parameters extracted from the measurement data. The operation voltage of NW CMOS inverter is reduced smaller than that of bulk CMOS due to the ideal sub-threshold slope. NW Tr. is highly promising for the ultra-low power and high-performance LSI applications.
- 公益社団法人 日本表面科学会の論文
公益社団法人 日本表面科学会 | 論文
- An XPS Analysis of the Interfacial Interaction between Oxides and Epoxy Resin.
- A Structure Analysis of Langmuir-Blodgett Magnetic Films by X-ray Diffraction.
- Structure and Reactivity of Surface Compounds Formed on Single Crystal Metal Surfaces During Catalytic Reactions.
- Atomic-Layer Etching of Si by Low Energy Ion Irradiation.
- Microstructure Observations of (Nd, Ce)2CuO4 Superconducting Thin Films by Using Cross-Sectional HRTEM and the Mechanism f Film Growth.