A smart method of optimizing the read/write current on PCM array
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概要
- 論文の詳細を見る
A method for optimizing the read/write current on phase change memory array is proposed. A smart current adjustment circuit is designed to bi-directionally alter the internal read/write current. The best read/write condition based on arrays can be found through this adjustment approach. Example of a 2-dimensional shmoo test on a 16k-bit phase change array implemented in 0.13 µm CMOS technology is given. The resistance distribution can also be roughly obtained. This method, taking advantage of the peripheral circuit, provides statistical yield data on a variety of read/write current, thus offering reliable and helpful indicators for chip parameter setup and process optimization.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Zhang Yiyun
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Wang Qian
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Song Zhitang
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Chen Houpeng
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Li Xi
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Jin Rong
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Wang Yuchan
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Cai Daolin
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
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Wang Yueqing
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences