Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
スポンサーリンク
概要
- 論文の詳細を見る
As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
-
NAKATAKE Shigetoshi
University of Kitakyushu
-
LI Jing
Design Algorithm Laboratory, Inc.
-
ZHANG Yu
University of Kitakyushu
-
CHEN Gong
University of Kitakyushu
-
YANG Bo
Design Algorithm Laboratory, Inc.
-
DONG Qing
University of Kitakyushu
-
LI Ming-Yu
University of Kitakyushu
関連論文
- Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver
- A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
- Regularity-Oriented Analog Placement with Conditional Design Rules
- An Incremental Wiring Algorithm for VLSI Layout Design
- Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing
- Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
- Structured Analog Circuit and Layout Design with Transistor Array