A Scalable, Fixed-Shuffling, Parallel FFT Butterfly Processing Architecture for SDR Environment

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概要

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• This paper presents a programmable and high-efficient application specific instruction-set processor (ASIP) for fast Fourier transformation (FFT) processing based on software defined radio (SDR) methodology. It adopts single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. The proposed ASIP features eight parallel radix-2 butterfly computations with fixed vector data shuffling pattern. In addition, a flexible vector address generation unit is proposed to support inner- and inter-group addressing mode. Experiment results show that the proposed FFT ASIP is much more flexible than previous works and outperforms state-of-the-art FFT ASIP architectures in term of energy-efficiency.

著者

• Chen Ting

  College of Computer, National University of Defense Technology

• Liu Hengzhu

  College of Computer, National University of Defense Technology

• Zhang Botao

  College of Computer, National University of Defense Technology

関連論文

• A Scalable, Fixed-Shuffling, Parallel FFT Butterfly Processing Architecture for SDR Environment

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