Highly Linear Low Voltage Low Power CMOS LNA

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概要

• 論文の詳細を見る

• A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching -1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.

著者

• Z.Kouzani Abbas

  School of Engineering, Deakin University Geelong

• Mafinezhad Khalil

  Department of Electrical Engineering Sadjad Institute for Higher Education

• Kargaran Ehsan

  Department of Electrical Engineering Sadjad Institute for Higher Education

• Zoka Negar

  Department of Electrical Engineering, Ferdowsi University

• Nabovati Hooman

  Department of Electrical Engineering Sadjad Institute for Higher Education

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• Highly Linear Low Voltage Low Power CMOS LNA

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