Low Power Design of Asynchronous Datapath for LDPC Decoder

概要

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We propose an asynchronous datapath for the low-density parity-check decoder to decrease power consumption. Glitches and redundant computations are decreased by the asynchronous design. Taking advantage of the statistical characteristics of the input data, we develop novel key arithmetic elements in the datapath to reduce redundant computations. Two other types of datapaths, including normal synchronous design and clock-gating design, are implemented for comparisons with the proposed design. The three designs use similar architectures and realize the same function by using the 0.18µm process of the Semiconductor Manufacturing International Corporation. Post-layout result shows that the proposed asynchronous design exhibits the lowest power consumption. The proposed asynchronous design saves 48.7% and 21.9% more power than the normal synchronous and clock-gating designs, respectively. The performance of the proposed datapath is slightly worse than the clock-gating design but is better than the synchronous design. The proposed design is approximately 7% larger than the other two designs.
The Institute of Electronics, Information and Communication Engineersの論文