A Delay Evaluation Circuit for Analog BIST Function

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概要

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• Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.

著者

• WANG Hong

  Automation Department, Tshinghua University

• MILOR Linda

  School of Electrical and Computer Engineering, Georgia Institute of Technology

• LV Zhengliang

  Automation Department, Tshinghua University

• YANG Shiyuan

  Automation Department, Tshinghua University

関連論文

• A Delay Evaluation Circuit for Analog BIST Function

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