A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

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概要

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• High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480MHz and the hardware cost is about 115.8K Gates. Experimental results show that the proposed architecture is able to deal with real-time HEVC IDCT/IDST of 4K×2K (4096×2048)@30fps video sequence at 171MHz in average. In consequence, it offers a cost-effective solution for the future UHDTV applications.

著者

• Hui Zhu

  School of Microelectronics, Shanghai Jiao Tong University

• Liang Hong

  School of Microelectronics, Shanghai Jiao Tong University

• Weifeng He

  School of Microelectronics, Shanghai Jiao Tong University

• Zhigang Mao

  School of Microelectronics, Shanghai Jiao Tong University

関連論文

• A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

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