A novel redundant pipelined successive approximation register ADC

概要

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This paper presents a 12-bit 100MS/s time-interleaved successive approximation register (SAR) ADC designed for intermediate frequency 3G receivers. The 12-bit 100MS/s 2-channel ADC with voltage-controlled delay lines (VCDLs) based time-domain comparator is designed in 65nm CMOS, single-channel 12-bit 50MS/s pipelined SAR ADC consists of a 6-bit MDAC first stage and a 7-bit SAR ADC second stage, the operational amplifier is shared between the two channels for low power dissipation. A novel redundant SAR ADC used in the first stage is proposed to avoid comparator offset issue. Moreover, tri-level flash-SAR ADC is proposed and used in the second stage, the total unit capacitors to realize a 7-bit tri-level flash-SAR ADC are 50% of the conventional two's complement flash-SAR architecture. Simulation results in 65nm CMOS process show that, the 12-bit 100MS/s ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 73.32dB (11.89 ENOB), a spurious free dynamic range (SFDR) of 90.65dB with a 2.7MHz input tone, while dissipating 10mW from a 1.2V supply.