A Fast-Locking Fractional-<I>N</I> Frequency Synthesizer using a New Variable Bandwidth Method
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概要
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A fast-locking fractional-<I>N</I> frequency synthesizer with a fourth-order PLL is presented for a receiver of multiple positioning systems. In order to reduce the locking time a new method of only performing LPF structure transformation is proposed, which exploits the large bandwidth without changing the charge-pump current during the transient state. The bandwidth of the third-order PLL with the second-order LPF during transient state is 10 times larger than that of the fourth-order PLL in the phase-locked state. Furthermore, a pre-charging circuit and the unchanged charge-pump current can significantly accelerate the phase locking. Simulation results show that the longest locking time is less than 10 µs in seven modes of three positioning systems (GPS, Galileo and Beidou). For each mode, the in-band and out-of-band phase noises are no larger than -93 dBc/Hz and -118.5 dBc/Hz, respectively, and the spurs are less than -56.4 dBc at 8.043MHz offset frequency. Total power consumption is 15.21 mW under 1.8V supply.
著者
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Feng Yan
The School of Electronic and Information Engineering, Xi'an Jiaotong University
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Chen Guican
The School of Electronic and Information Engineering, Xi'an Jiaotong University
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Xu Jiangtao
The School of Electronic and Information Engineering, Xi'an Jiaotong University
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Wu Minshun
The School of Electronic and Information Engineering, Xi'an Jiaotong University
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Wu Minshun
The School of Electronic and Information Engineering, Xi'an Jiaotong University
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Xu Jiangtao
The School of Electronic and Information Engineering, Xi'an Jiaotong University