Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects

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概要

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• Microwave interconnects have been proposed recently to break-down long wires in large integrated circuits. In this paper, using of coplanar waveguide RF interconnects in FPGAs is explored to improve performance and reduce routing congestion. We propose a new FPGA architecture consisting of both metal wires and RF receivers/transmitters corresponding with an algorithm to route the proposed FPGA. Experimental results show that used routing tracks and routing congestion are reduced by 23.8% and 7.06%, respectively and performance of the attempted benchmarks is improved by about 33% using this technique. These benefits are earned in reasonable cost of area and power consumption which is negligible for large and complex circuits.

著者

• DOKHANCHI Adel

  Arizona State University

• TEIMOORI Mohammad

  Shahid Beheshti University

• JAHANIAN Ali

  Shahid Beheshti University

関連論文

• Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects

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