Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

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概要

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• This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

著者

• Nakata Yohei

  Depratment of Information science Kobe University

• Okumura Shunsuke

  Depratment of Information science Kobe University

• Yanagida Koji

  Depratment of Information science Kobe University

• Kagiyama Yuki

  Depratment of Information science Kobe University

• Yoshimoto Shusuke

  Depratment of Information science Kobe University

• Kawaguchi Hiroshi

  Depratment of Information science Kobe University

• Yoshimoto Masahiko

  Depratment of Information science Kobe University

関連論文

• Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

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