Scan power reduction based on clock-gating

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概要

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• The paper presents a new methodology to reduce scan test power by means of clock-gating. Scan-shift power is reduced through not clocking certain scan chains when they finish load/unload and scan-capture power reduction can be implemented by not clocking the scan chains in which there is no observation point. In addition, the corresponding hardware design is presented so as to show the feasibility of the new methodology. The algorithm for scan pattern reordering is also proposed to maximize the reduction of scan-shift power under certain constraint. Experimental results on several industrial designs have shown the effectiveness of this new methodology.

著者

• Huang Ning

  Institute of RF- & OE-ICs, Southeast University

• Zhu En

  Institute of RF- & OE-ICs, Southeast University

関連論文

• Scan power reduction based on clock-gating

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