A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers

概要

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A low-power low-noise intermediate-frequency (IF) circuit is proposed for Gaussian frequency shift keying (GFSK) low-IF receivers. The proposed IF circuit is realized by an all-analog architecture composed of a couple of limiting amplifiers (LAs) and received signal strength indicators (RSSIs), a couple of band-pass filters (BPFs), a frequency detector (FD), a low-pass filter (LPF) and a slicer. The LA and RSSI are realized by an optimized combination of folded amplifiers and current subtractor based rectifiers to avoid the process induced depressing on accuracy. In addition, taking into account the nonlinearity and static current of rectifiers, we propose an analytical model as an accurate approximation of RSSIs transfer character. An active-RC based GFSK demodulation scheme is proposed, and then both low power consumption and a large dynamic range are obtained. The chip is implemented with HJTC 0.18µm CMOS technology and measured under an intermediate frequency of 200kHz, a data rate of 100kb/s and a modulation index of 1. The RSSI has a dynamic range of 51dB with a logarithmic linearity error of less than ±1dB, and the slope is 23.9mV/dB. For 0.1% bit error ratio (BER), the proposed IF circuit has the minimum input signal-to-noise ratio (SNR) of 5dB and an input dynamic range of 55.4dB, whereas it can tolerate a frequency offset of -3%∼+9.5%% at 6dB input SNR. The total power consumption is 5.65∼5.89mW.