On the efficient computation of single-bit input word length pipelined FFTs

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概要

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• This letter describes an efficient architecture for the computation of fast Fourier transform (FFT) algorithms with single-bit input. The proposed architecture is aimed for the first stages of pipelined FFT architectures, processing one sample per clock cycle, hence making it suiable for real-time FFT computation. Since natural input order pipeline FFTs use large memories in the early stages, it is important to keep the word length shorter in the beginning of the pipeline. By replacing the initial butterflies and rotators of an architecture with that of the proposed block, the memory requirements can be significantly reduced. Comparisons with the commonly used single delay feedback (SDF) architecture show that more than 50% of the required memory can be saved in some cases.

著者

• Gustafsson Oscar

  Department Of Electrical Engineering Linkoping University

• Qureshi Fahad

  Department Of Electrical Engineering Linkoping University

• Athar Saima

  Department of Electrical Engineering Linköping University

• Kale Izzet

  Applied DSP and VLSI Research Group University of Westminster

関連論文

• Comments on 'A 70MHz Multiplierless FIR Hilbert Transformer in 0.35μm Standard CMOS Library'
• On the efficient computation of single-bit input word length pipelined FFTs
• Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs

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