Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes
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概要
- 論文の詳細を見る
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC codes Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.
著者
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Sun Rong
State Key Lab Of Isn Xidian University
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MU Jianjun
School of Computer Science and Technology, Xidian University
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MU Jianjun
School of Computer Science and Technology, Xidian University, State Key Laboratory of Integrated Service Networks, Xidian University
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JIAO Xiaopeng
School of Computer Science and Technology, Xidian University, State Key Laboratory of Integrated Service Networks, Xidian University
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LIU Jianguang
School of Computer Science and Technology, Xidian University, State Key Laboratory of Integrated Service Networks, Xidian University
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JIAO Xiaopeng
School of Computer Science and Technology, Xidian University
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