Model of Network-on-Chip routers and performance analysis

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概要

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• This paper presents a generic analytical performance model of Network-on-Chip (NoC) router, which is further used to analyze the performance of a whole wormhole NoC. We focus on the analysis of various packet blocking-conditions at the router input-queues for a more accurate estimation of waiting time. Based on this estimation, some key performance metrics of NoC, such as the buffer utilization and packet transfer latency, are both computed. Compared with some previous model, it presents more accurate results: for buffer utilization ratio, the error is 6.30%; for packet transfer latency, it is about 5.98%.

著者

• Zheng Weimin

  Department Of Computer Science And Technology Tsinghua University

• Zhang Youhui

  Department Of Computer Science And Technology Tsinghua University

• Dong Xiaoguo

  Department of Mathematical Science and Computing Technology, Central South University

• Gan Siqing

  Department of Mathematical Science and Computing Technology, Central South University

関連論文

• Codec-on-Demand Based on User-Level Virtualization
• Model of Network-on-Chip routers and performance analysis

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