Fully parallel comparator for the moduli set {2n,2n-1,2n+1}

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概要

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• A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.

著者

• Hosseinzadeh Mehdi

  Science and Research Branch, Islamic Azad University

• Mirmotahari Omid

  Nanoelectronic System Group at the Department of Informatics, University of Oslo

• Eivazi Shiva

  Department of Computer Engineering, Science and Research Branch, Islamic Azad University

関連論文

• Fully parallel comparator for the moduli set {2n,2n-1,2n+1}
• A new four-moduli set with high speed RNS arithmetic unit and efficient reverse converter
• Reverse converter for the flexible moduli set {2n+k, 22n-1-1, 2n/2+1, 2n/2-1}

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