Electrical characteristics and thermal reliability of BJT-inserted GSTNMOS using the 65nm CMOS process

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概要

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• This paper presents a NMOS-based ESD protection circuit with a low trigger voltage using the 65-nm CMOS process. The proposed ESD protection circuit is achieved by using a gate-substrate triggered technique. We measured the I-V characteristics, temperature characteristics and leakage current under normal operating conditions. The results of the ESD protection circuit were validated using a transmission line pulse (TLP) system. Also, the temperature range from 300K to 500K facilitates the understanding of physical mechanisms for the ESD protection circuits reliability. From the results, this structure not only exhibited a lower trigger voltage but also has a lower leakage current.

著者

• Koo Yong

  Department of Electronics & Electrical Engineering, University of Dankook

関連論文

• Electrical characteristics and thermal reliability of BJT-inserted GSTNMOS using the 65nm CMOS process
• SCR-based ESD protection device with low trigger and high robustness for I/O clamp
• Design of high-reliability LDO with current limiting characteristics with built-in New high tolerance ESD protection circuit
• Erratum: Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit [IEICE Electronics Express Vol. 10 (2013) No. 20 pp. 20130516]

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