A Novel Post-Silicon Debug Mechanism Based on Suspect Window
スポンサーリンク
概要
- 論文の詳細を見る
Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS89 and ITC99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability.
著者
-
GAO Jianliang
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade
-
HAN Yinhe
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade
-
LI Xiaowei
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade
関連論文
- A Novel Post-Silicon Debug Mechanism Based on Suspect Window
- Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
- A Novel Post-Silicon Debug Mechanism Based on Suspect Window
- Testable Critical Path Selection Considering Process Variation
- Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power