A high CMRR low power fully differential Current Buffer

概要

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In this paper a low power fully differential current buffer is introduced which performs high CMRR exploiting a novel method to alleviate common mode gain. The proposed current buffer is designed and simulated with HSPICE in 0.18µm CMOS process and supply voltage of ±0.75V. The simulation results show an 8.48Ω input resistance, 98dB CMRR, 369MHz bandwidth and power dissipation of 135µW. The corner case simulation has been done which shows an acceptable performance for the proposed buffer in all situations. The proposed circuit tends to be the fundamental block of a new family of electronic differential topologies greatly capable to be much further improved and utilized.