Fully digital clock frequency doubler

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概要

• 論文の詳細を見る

• This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650MHz to 1.25GHz.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Son Jae

  SOC Platform Team, Samsung Electronics

• Jung Gunok

  SOC Platform Team, Samsung Electronics

• Park Gi-Ho

  Department of Computer Engineering, Sejong University

• Cho Ukrae

  SOC Platform Team, Samsung Electronics

関連論文

• Fully digital clock frequency doubler

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