Efficient FPGA implementation of sharp FIR filters using the FRM technique

スポンサーリンク

概要

• 論文の詳細を見る

• A high-performance field programmable gate array (FPGA) implementation of full pipelined computation structure is proposed for sharp finite-impulse -response (FIR) filters using the frequency response masking (FRM) technique. The FRM-based FIR (FFIR) filter consists of a novel symmetrical systolic array of a interpolated FIR(IFIR) filter in cascade to a pair of nonsymmetrical systolic arrays of masking FIR filters mainly. These filters are designed based on inner-product computation involving MAC operation which can be realized by the DSP block in the latest FPGA device efficiently. The realization results on a Xilinx Virtex-5 chip show that the proposed FPGA implementation can obtain higher throughput but consumes less resource compared to the equivalent conventional sharp FIR (CSFIR) filter that developed by the Core Generator software tool.

著者

• Li Shuguo

  Institute of Microelectronics, Tsinghua University

• Zhang Jian

  Institute of Microelectronics, Tsinghua University

関連論文

• Data-recovery algorithm and circuit for cyclic convolution based on FNT
• Efficient FPGA implementation of sharp FIR filters using the FRM technique
• The Effect of Different Species Aminopeptidase N Structure on the Activity Screening of Aminopeptidase N Inhibitor
• Opposing effects of interferon-α and interferon-γ on the expression of major histocompatibility complex class I chain-related A in tumors
• Cisplatin up-regulates ICAM-1 expression in endothelial cell via a NF-κB dependent pathway
• Spatial variation of species diversity across scales in an old-growth temperate forest of China

スポンサーリンク