Implementation of a multi-rate and multi-size LDPC decoder

概要

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A fully reconfigurable architecture of a LDPC (low-density parity check) decoder for IEEE 802.11n system is proposed in this paper. This architecture can be operated in 12 kinds of modes specified in IEEE 802.11 system. Under the proposed architecture, memory usage and hardware complexity obviously improved, as compared with the other research works. Furthermore, the proposed decoder also able to support multi-rate and multi-size LDPC codes decoding. The proposed decoder was implemented in UMC 0.18µm CMOS technology. The maximum operating frequency is measured 200MHz and the corresponding power dissipation is 691.23mW and total area is 4.61mm2.