A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs

概要

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A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement.