A novel low power time-mode comparator for successive approximation register ADC

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概要

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• A novel low power time-mode comparator with enhanced resolution and speed is proposed in this paper. The comparator incorporates a symmetrical input time-to-digital converter (TDC) and a highly dynamic voltage-to-time converter (VTC). Energy reduction is achieved mainly through the use of capacitor discharge automatic switch-off and inverter clocking. The combined effect of the low timing requirement and capacitor voltage presetting enables significant precision and speed improvements. Simulations in a 0.18um process show that the comparator can be clocked at 38MHz, draws less than 0.4pJ energy from supply and can resolve voltages as low as 10µV.

著者

• Kobenge Sekedi

  Electronic Engineering Department, TNLIST, Tsinghua University

• Yang Huazhong

  Electronic Engineering Department, TNLIST, Tsinghua University

関連論文

• A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator
• A novel low power time-mode comparator for successive approximation register ADC

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