On the design of low power 1-bit full adder cell
スポンサーリンク
概要
- 論文の詳細を見る
A 1-bit full adder cell based on majority function is designed and simulated. In this design the time consuming XOR gates are eliminated. Low-power consumption is targeted in implementation of our design. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The new circuit has been compared to the previous work based on power consumption, speed and power delay product (PDP). HSPICE and Cadence simulations show that the proposed adder can work more reliably at different range of supply voltage. The proposed design has the best PDP in comparison with the others.
著者
-
Navi Keivan
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC
-
Navi Keivan
Faculty of Electrical and Computer Engineering, Shahid Beheshti University
-
Maeen Mehrdad
Department of Computer Engineering, Science and Research Branch, Islamic Azad University
-
Foroutan Vahid
Department of Computer Engineering, Science and Research Branch, Islamic Azad University
関連論文
- On the design of low power 1-bit full adder cell
- High speed reverse converter for new five-moduli set {2n, 22n+1-1, 2n/2-1, 2n/2+1, 2n+1}
- Efficient RNS to binary converters for the new 4-moduli set {2n, 2n+1-1, 2n-1, 2n-1-1}