Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects

概要

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Bumpless interconnects prospected to the Tera-byte large scale integration using three-dimensional (3D) processes has been discussed. The key feature of bumpless as well as no bump interconnects is a second-generation alternative to the use of micro-bump for Wafer-on-Wafer (WOW). In our 3D interconnects technology is classified into Via-Last from the front side and stacking Back-to-Front in which any number of thinned 300 mm wafers and/or heterogeneous dies can be stacked realizing further large-scale devices with low cost rather than the use of extreme ultraviolet (EUV) lithography which will be expected at 18〜22 nm and beyond. In the economic sense in many situations, WOW is the leading-edge process among 3D processes because stacking at the wafer level drastically increases the processing throughput and bumpless interconnects provide an appropriate yield using existing technology which is equivalent to or greater than that achievable with 2D scaling beyond 22 nm nodes. This paper is described by our recent studies as shown in references.
一般社団法人電子情報通信学会の論文
2013-07-25