Compact Codes of Slicing Floorplans

概要

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A floorplan is a partition (dissection) of a rectangle into small rectangles, called blocks, by horizontal and vertical line segments such that no four rectangles meet at the same point. Floorplans are used to design the layout of very-large-scale integration (VLSI) circuits. Since modern VLSI circuits are extremely large, it is necessary to design a compact representation of floorplans. Slicing floorplans are one of important classes of floorplans. It is also desirable to design a compact representation of the slicing floorplans. We therefore address a problem of designing compact code for the slicing floorplans. We first propose a code for a slicing floorplan of 3n - 3 bits. We then propose a more compact code for a slicing floorplan. Finally, we experimentally compare the two codes.
2014-06-06