A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule

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概要

• 論文の詳細を見る

• In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel deltavalue based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418 Mbps at the frequency of 200 MHz.

• 一般社団法人情報処理学会の論文
• 2009-02-17

著者

• Takeshi Ikenaga

  Graduate School of Information, Production and Systems, Waseda University

• Satoshi Goto

  Graduate School of Information, Production and Systems, Waseda University

• Wen Ji

  Graduate School of Information, Production and Systems, Waseda University

• Xing Li

  Graduate School of Information, Production and Systems, Waseda University | Presently with NEC Electronics Corporation

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• A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule

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